With integrated circuits becoming smaller and faster, the improvement in device driving currents of metal-oxide-semiconductor (MOS) devices becomes increasingly more important. Device current is closely related to gate length, gate capacitance, and carrier mobility. Shortening poly-gate length, increasing gate capacitance, and increasing carrier mobility can improve the device current performance. Gate length reduction is an on-going effort coming with the effort to shrink circuit size. Increasing gate capacitance has also been achieved by efforts such as reducing the gate dielectric thickness, increasing the gate dielectric constant, and the like. In order to further improve device current, enhancing carrier mobility has also been explored.
Among efforts made to enhance the carrier mobility, forming stressed channels is a known practice. Stress can enhance bulk mobility of electrons and holes, and hence the performance of MOS devices can be enhanced through stressed-surface channels. This technique allows the performance of MOS devices to be improved at a constant gate length, without adding complexity to circuit fabrication or design.
When silicon is placed under stress, the in-plane, room temperature electron mobility is dramatically increased. One way to develop stress is by using a graded SiGe epitaxy layer as a substrate on which a layer of relaxed SiGe is formed. A layer of silicon is formed on the relaxed SiGe layer. MOS devices are then formed on the silicon layer, which has an inherent stress. Since the lattice constant of SiGe is greater than that of Si, the Si film is under biaxial tension and thus the carriers exhibit stress-enhanced mobility.
Stress in a device may have components in three directions: parallel to the MOS device channel length, parallel to the device channel width, and perpendicular to the channel plane. The stresses parallel to the device channel length and width are called in-plane stresses. Research has revealed that a bi-axial, in-plane tensile stress field can improve the performance of n-type MOS (NMOS), and a compressive stress parallel to the channel length direction can improve the performance of p-type MOS (PMOS device).
Typically, STI regions apply compressive stresses to the channel regions of nearby MOS devices. This is beneficial to the PMOS devices while detrimental to the NMOS devices. In further explorations, local mechanical stress-control technologies have been reported to improve device performance of NMOS devices by using sub-atmospheric chemical vapor deposition (SACVD) to form shallow trench isolation regions. Since the high-shrinkage material in the STI regions reduce the adverse compressive stress applied to the channel regions of NMOS device, the degradation in the performance of NMOS devices is less severe. Other methods to increase desirable stresses or to reduce undesirable stresses in the channel regions are also needed.